1. Field of the Invention
This invention relates to semiconductor device manufacturing, and more particularly, to an improved oxide-nitride layer and a method for making the same.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
The formation of oxide layers upon silicon layers is commonly used within fabrication processes of a variety of semiconductor devices. Sometimes, however, irregularities may exist within the silicon surface or may be created during the formation of the oxide layer, both of which may bring about a disjointed oxide pattern which can lead to dangling bonds, often referred to as xe2x80x9cinterface trapsxe2x80x9d at the oxide-silicon interface. Dangling-bonds are generally sporadic silicon-to-oxide atomic bonds, which readily accept mobile carriers (electrons or holes) at the oxide-silicon interface. The build-up of mobile carriers may generate high electric fields across the oxide layer and the continual passage of charge across the tunnel oxide region of a device. Consequently, interface traps may cause a variety of problems, such as shifts in the threshold voltage (Vt) of an ensuing device and/or breakdown of the oxide layer. In addition, the build-up of mobile carriers may increase the back tunneling current of non-volatile semiconductor memory cells, thereby dissipating the memory of the cells more quickly. Consequently, the presence of interface traps may degrade the long-term retention of non-volatile memory cells.
In some cases, interface traps within fabricated devices may be passivated such that the build-up of mobile carriers are reduced or eliminated for an amount of time, thereby theoretically improving device reliability. In particular, the silicon-to-oxide atomic bonds within an oxide-silicon interface may be made stronger to withstand the operation of the device for a longer period of time. For example, in some cases, devices may be annealed in hydrogen (H2) to passivate interface traps. In other embodiments, devices may be annealed in deuterium (D2) to passivate interface traps. Such anneals are typically performed subsequent to the formation of the device, such as after a contact or bond pad etch.
Although using hydrogen or deuterium anneals may passivate interface traps of fabricated devices, using such anneals may present problems affecting the functionality and reliability of the devices. In particular, such anneal processes typically require the use of xe2x80x9cpurexe2x80x9d hydrogen (H2) or deuterium (D2). xe2x80x9cPurexe2x80x9d hydrogen and deuterium may refer to gases, which are free or substantially absent of other elements. Typically, free hydrogen and free deuterium include safety hazards, which make them difficult to incorporate into semiconductor fabrication processes. In particular, free hydrogen and free deuterium are both considered explosion hazards when used at temperatures greater than approximately 500xc2x0 C. or exposed to oxygen. The temperature required for deuterium anneals, however, is typically between 500xc2x0 C. and 700xc2x0 C. Such a high temperature along with an annealing duration between approximately 4 to 5 hours, which is typically required for deuterium anneals, may severely degrade metallization with a device and/or cause certain dielectric materials to reflow. Moreover, such an anneal process may undesirably increase the thermal budget of a fabrication process, degrading the functionality of devices fabricated therefrom. In addition, deuterium cannot diffuse through nitride. Consequently, the use of a deuterium anneal in devices, which include nitride layers, such as SONOS devices, are limited in their capability to improve device reliability.
It would therefore be desirable to develop a safe and non-destructive method for passivating dangling bonds within a lower oxide-silicon interface of a SONOS structure. In particular, it may be desirable to develop a method for diffusing deuterium into a lower oxide-silicon interface of a SONOS structure.
The problems outlined above may be in large part addressed by a method for processing a semiconductor topography, which includes diffusing deuterium across one or more interfaces of a silicon-oxide-nitride-oxide-silicon (SONOS) structure. In particular, the method may include diffusing deuterium across one or more layer interfaces of a SONOS structure during a reflow of a dielectric layer spaced above the SONOS structure. In some embodiments, the method may include forming a deutereated nitride layer above the SONOS structure prior to the reflow process. In addition or alternatively, the method may include forming a deutereated nitride layer within the SONOS structure prior to the reflow process. In some cases, the method may further include annealing the SONOS structure with a deutereated substance prior to forming the deutereated nitride layer. In either embodiment, a SONOS structure may be formed which includes deuterium arranged within an interface of a silicon layer and an oxide layer of the structure.
As stated above, a method for processing a semiconductor topography is provided herein which includes diffusing deuterium across one or more layer interfaces of a SONOS structure during a reflow of a dielectric layer spaced above the SONOS structure. For example, in some embodiments, the method may include diffusing deuterium across an interface between a lower silicon layer and a lower oxide layer of a SONOS structure. In other embodiments, the method may additionally or alternatively include diffusing deuterium across an interface between an upper silicon layer and an upper oxide layer of the SONOS structure. In yet other embodiments, the method may include diffusing deuterium across an interface between either of the lower or upper oxide layers and a nitride layer of the SONOS structure. Furthermore, in some cases, the method may include introducing deuterium into at least one of the one or more layer interfaces. In other words, the method may include introducing deuterium into at least one interface that did not previously contain deuterium.
In either embodiment, the method may include forming a deutereated nitride layer prior to the reflow process. In some embodiments, the method may include forming a deutereated nitride layer within the SONOS structure. In such an embodiment, the method may include forming the deutereated nitride layer upon an oxide-silicon bilayer stack and forming a second oxide-silicon stack above the deutereated nitride layer to form a SONOS structure. In addition or alternatively, method may include forming a deutereated nitride layer above the SONOS structure. In either embodiment, forming the deutereated nitride layer may include depositing the nitride layer in an ambient including a deutereated substance, such as deutereated ammonia. In some cases, the method may include annealing the semiconductor topography prior to forming the deutereated nitride layer. Such an anneal process may include introducing deuterium into the semiconductor topography. In particular, the anneal process may include introducing deuterium into an upper portion of the semiconductor topography. As such, in some embodiments, the method may include annealing the semiconductor topography with a deutereated substance, such as deutereated ammonia, for example.
In addition, the method may include depositing a dielectric layer above the deutereated nitride layer prior to the reflow process. In particular, the method may include depositing a dielectric layer above the SONOS structure prior to the reflow process. In some embodiments, the dielectric layer may be deposited as a deutereated dielectric. In other embodiments, the dielectric layer may be deposited substantially absent of deuterium. In either embodiment, the method may further include reflowing the dielectric layer such that one or more interfaces of the SONOS structure may be diffused with deuterium. Such a reflow process may include exposing the semiconductor topography to steam, in some embodiments. In other embodiments, the reflow process may include exposing the semiconductor topography to an ambient including a deutereated substance.
Consequently, a SONOS structure is contemplated herein which includes a first silicon layer with an undoped lower portion and a first oxide layer arranged upon the first silicon layer. In some embodiments, the first silicon layer may include a silicon substrate, such as a monocrystalline substrate. The first oxide layer, on the other hand, may include an oxide material, such as deposited or thermally grown silicon dioxide. Regardless of the composition of the first silicon layer and first oxide layer, an interface between the first silicon layer and first oxide layer may include deuterium, in some embodiments. In addition, the SONOS structure may include a deutereated nitride layer arranged upon and in contact with the first oxide layer. In some embodiments, the deutereated nitride may include deutereated silicon nitride. In addition or alternatively, an interface between the first oxide layer and the nitride layer may include deuterium in some cases. Furthermore, the SONOS structure may include a second oxide layer arranged upon and in contact with the deutereated nitride layer. In some cases, the interface between the second oxide layer and the nitride layer may include deuterium. Moreover, the SONOS structure may include a second silicon layer arranged upon and in contact with the second oxide layer. Such a second silicon layer may include doped polysilicon in some embodiments.
There may be several advantages to processing a semiconductor topography according to the method described herein. For example, deuterium may be diffused across an oxide-silicon interface such that dangling bonds within the interface may be passivated. In this manner, the endurance and retention of devices fabricated by the method described herein may be improved. In addition, dangling bonds of devices including nitride layers, such as SONOS devices, may be passivated. Moreover, the method described herein may not cause damage to the metallization or interlevel dielectrics of devices. In addition, the method may not substantially increase the thermal budget of devices. In this manner, the functionality and reliability of devices may not be degraded. Furthermore, annealing in an ambient of pure deuterium may be avoided, thereby reducing the safety hazards of semiconductor fabrication processes.